LOGIC DEVICE AND METHOD SUPPORTING SCAN TEST

专利名称：LOGIC DEVICE AND METHOD SUPPORTING

SCAN TEST

发明人：SAINT-LAURENT, MARTIN,BASSETT,

PAUL,PATEL, PRAYAG

申请号：US2007071450申请日：20070618

公开号：WO2007149808A3公开日：20080207

摘要：A logic device includes a data input, a scan test input, a clock demultiplexer, anda master latch. The clock demultiplexer is responsive to a clock input to selectivelyprovide a first clock output and a second clock output. The master latch is coupled to thedata input and to the scan test input and includes an output. The master latch isresponsive to the first clock output of the clock demultiplexer and the second clockoutput of the clock demultiplexer to selectively couple the data input or the scan testinput to the output.

申请人：QUALCOMM INCORPORATED,SAINT-LAURENT, MARTIN,BASSETT,PAUL,PATEL, PRAYAG

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